PCI Express is a plug-and-play protocol meaning that after power-up, the PCIe Host (root complex) will enumerate the system. In this process, the host assigns a base address and a memory space to each PCIe device connected to the bus (endpoints) as indicated in the configuration space of each device.
PCIe endpoint devices must be ready when the host queries them or they will not get a base address and therefore, will not be accessible from the host. According to PCI Express specification, the PERST signal (which is the PCI Express card reset) must deassert 100 ms after the power-up of the systems has occurred. Moreover, the PCI Express port must be ready for link training no more than 20 ms after the PERST signal has deasserted. This is commonly known as the 100 ms boot time requirement.
In the case of FPGAs, the configuration process from a PROM can take more than 100 ms. The configuration time depends on the size of the bitstream, the clock frequency of the PROM memory, and the configuration bus width but it is quite common for this process to take more than 100ms on medium/large FPGAs.
Tandem Configuration in Xilinx FPGAs utilizes a two-stage methodology that enables the device to meet the configuration time requirements indicated in the PCI Express specification. Multiple-use cases are supported by this technology but they are based on the same principle, the PCIe interface is configured in less than 100ms using part of a bitstream or a full bitstream (of small size) which contains what is strictly necessary to allow the host to recognize it. This configuration file is stored in the PROM.
Once the device has been correctly enumerated, the rest of the design can be loaded into the FPGA through the second part of the bitstream stored in the PROM (tandem PROM) or through a second bitstream which is sent from the host by using the PCIe bus (tandem PCIe).
Another option is not to use Tandem and when the Host finishes booting and the FPGA finishes programming, enumerate the PCIe bus again to find new devices like the FPGA. For this purpose, the host must enable the HotPlugPCIe capability.
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